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April 1999
ML6692 100BASE-TX Physical Layer with MII
GENERAL DESCRIPTION
The ML6692 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6692 interfaces to the controller through the standard-compliant Media Independent Interface (MII). The ML6692 functionality includes auto-negotiation, 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3/ 10BASE-T transmitter. For applications requiring 100Mbps only, such as repeaters, the ML6692 offers a single-chip per-port solution. For 10/100 dual speed adapters or switchers, 10BASE-T functionality may be attained using Micro Linear's ML2653, or by using an Ethernet controller that contains an integrated 10BASE-T PHY.
FEATURES
s s s s
Single-chip 100BASE-TX physical layer Compliant to IEEE 802.3u 100BASE-TX standard Supports adapter, repeater and switch applications Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY Compliant MII (Media Independant Interface) Auto-negotiation capability 4B/5B encoder/decoder Stream Cipher scrambler/descrambler 125MHz clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation
s s s s s s s s
BLOCK DIAGRAM
1 9
(PLCC Package)
49 48
CLOCK SYNTHESIZER
TXCLK
3 4 5 6 7 8 18 19 17 10 12 14 16 21 23 24 25
TXD3 TXD2 TXD1 TXD0 TXEN TXER CRS COL RXCLK RXD3 RXD2 RXD1
PCS TRANSMIT STATE MACHINE 4B/5B ENCODER SCRAMBLER NRZ TO NRZI ENCODER SERIALIZER MLT-3 ENCODER FLP/100BASE-TX/10BASE-T TWISTED PAIR DRIVER
10BTTXINP
TXCLKIN
10BTTXINN
TPOUTP TPOUTN RTSET
40 39 37
CARRIER AND COLLISION LOGIC
CLOCK AND DATA RECOVERY NRZI TO NRZ DECODER DESERIALIZER
EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX
TPINP TPINN CMREF RGMSET LINK100
45 44 46 36 43
PCS RECEIVE STATE MACHINE 5B/4B DECODER
RXD0 RXDV RXER DESCRAMBLER
AUTO-NEGOTIATION AND CONTROL LOGIC 10BTLNKEN
INITIALIZATION REGISTER
10BTRCV
MDIO
T4FAIL
MII MANAGEMENT REGISTERS
29
30
50
51
SEL10HD
T4EN
EDIN
MDC
47
31
32
33
SEL10FD /ECLK
35
SEL100T4 /EDOUT
DUPLEX
1
ML6692
PIN CONFIGURATION
ML6692 52-Pin PLCC (Q52)
TXEN TXD0 TXD1 TXD2 TXD3 AGND1 TXCLKIN AVCC1 10BTLNKEN 10BTRCV 10BTTXINP 10BTTXINN DUPLEX
7 6 5 4 3 2 1 52 51 50 49 48 47 TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS COL DGND3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 46 45 44 43 42 41 40 39 38 37 36 35 34 CMREF TPINP TPINN LINK100 AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET SEL100T4/EDOUT AVCC3
2
RXDV DVCC2 RXER MDC MDIO DGND4 DVCC5 DGND5 T4EN T4FAIL EDIN SEL10HD SEL 10FD/ECLK
TOP VIEW
ML6692
PIN CONFIGURATION
ML6692 64-Pin TQFP (H64-10)
10BTLNKEN 10BTTXINP 10TTXINN AGND1A AGND1B TXCLKIN 10TRCV AVCC1
TXD0
TXD1
TXD2
TXD3
TXEN
TXER
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TXCLK RXD3 DGND1A DGND1B RXD2 DVCC1A DVCC1B RXD1 DGND2A DGND2B RXD0 RXCLK CRS COL DGND3A DGND3B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DUPLEX CMREF TPINP TPINN LINK100 AVCC2 AGND2A AGND2B TPOUTP TPOUTN AGND3A AGND3B RTSET RGMSET SEL100T4/EDOUT AVCC3
MDC
DGND4A
DVCC5A
MDIO
DGND4B
DVCC5B
DGND5A
T4EN
T4FAIL
DGND5B
EDIN
SEL10HD
TOP VIEW
SEL10FD/ECLK
DVCC2
RXDV
RXER
NC
3
ML6692
PIN DESCRIPTION
PIN NAME
(Pin Numbers for TQFP package in parentheses)
FUNCTION
1 (56)
TXCLKIN
Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels. Analog ground. Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data appearing at TXD<3:0> are clocked into the ML6692 on the rising edge of TXCLK. Transmit enable TTL input. Driving this input high indicates to the ML6692 that transmit data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK. Transmit error TTL input. Driving this pin high with TXEN also high causes the part to continuously transmit scrambled H symbols. When TXEN is low, TXER has no effect. Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6692 on the rising edge of this clock. Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK's rising edge. Digital ground. Digital +5V power supply. Digital ground. Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive data at RXD<3:0> changes on the falling edges and should be sampled on the rising edges of this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX signal is not present at TPINP/N. Carrier Sense TTL output. For 100Mbps operation in standard mode, CRS goes high in the presennon-idle signals at TPINP/N, or when the ML6692 is transmitting. CRS goes low when there is no transmit activity and receive is idle. For 100 Mbps operation in repeater mode or half duplex mode, CRS goes high in the presence of non-idle signals at TPINP/N only. Collision Detected TTL output. For 100 Mbps operation COL goes high upon detection of a collision on the network, and remains high as long as the collision condition persists. COL is low when the ML6692 operates in either full duplex, or loopback modes. Digital ground. Receive data valid TTL output. This output goes high when the ML6692 is receiving a data packet. RXDV should be sampled synchronously with RXCLK's rising edge. Digital +5V power supply. Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER should be sampled synchronously with RXCLK's rising edge. MII Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6692's MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz.
2 (57, 58) 3, 4, 5, 6, (59, 60, 61, 62) 7 (63) 8 (64) 9 (1)
AGND1 TXD<3:0> TXEN TXER TXCLK
10, 12, 14, 16 (2, 5, 8, 11) 11 (3, 4) 13 (6, 7) 15 (9, 10) 17 (12)
RXD<3:0> DGND1 DVCC1 DGND2 RXCLK
18 (13)
CRS
19 (14)
COL
20 (15, 16) 21 (17) 22 (18) 23 (19)
DGND3 RXDV DVCC2 RXER
24 (20)
MDC
4
ML6692
PIN DESCRIPTION
PIN NAME
(Continued)
FUNCTION
25 (21)
MDIO
MII Management Interface data TTL input/output. Serial data are written to and read from the ML6692's management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Data output should be sampled synchronously with MDC's rising edge. Digital ground. Digital +5V power supply. Digital ground. 100BASE-T4 enable TTL output. This output goes low if the auto-negotiation function chooses 100BASE-T4 as the highest common denominator technology. This output is high on power-up, during auto-negotiation, when the ML6692 enables any other protocol, or when 100BASE-T4 technology is not supported. If auto-negotiation is disabled, T4EN is always low. 100BASE-T4 link fail TTL input. When driven high, it indicates a good, 100BASE-T4 link. When the auto-negotiation function chooses 100BASE-T4 as the highest common denominator technology, and indicates it by driving T4EN low, T4FAIL should go high within 750-1000ms; otherwise auto-negotiation is restarted. Driving this pin low after autonegotiation is completed, also restarts it. In the parallel detection function, driving this pin high indicates that the 100BASE-T4 link is ready. If auto-negotiation is disabled and management register bit 0.13 is set to 1 (100Mb/s data rate selected), driving T4FAIL high indicates a valid 100BASE-T4 link and disables the ML6692's 100BASE-TX analog functions. If bit 13 of the MII Control register is set to 0, T4FAIL has no effect. Initialization interface mode select and EEPROM interface mode data-in CMOS input/output. EDIN selects one of three possible interface modes at power up. See table on page 14 for more detail Initialization Interface 10BASE-T half duplex CMOS input. When EDIN is high or floating, this pin has no effect. When EDIN is low, this pin sets the value of bit 11 of the MII Status register (10Mb/s half duplex), and the default value of bit 5 of the MII Advertisment register (10BASE-T half duplex capability). Initialization Interface 10BASE-T full duplex CMOS input/clock CMOS input/output. ECLK When EDIN is low, this pin sets the value of bit 12 of the MII Status register (10Mb/s full duplex), and the default value of bit 6 of the MII Advertisement register (10BASE-T full duplex capability). When EDIN is left floating, this pin provides the output clock to read initialization data from an external EEPROM. When EDIN is high, this pin is the input clock to load data from an external microcontroller. Analog +5V power supply. Initialization Interface 100BASE-T4 CMOS input and EEPROM or microcontroller data-out CMOS input. When EDIN is low, this pin sets the value of bit 15 of the MII Status register (100BASE-T4), and the default value of bit 9 of the MII Advertisement register (100BASE-T4 capability). When EDIN is floating, this pin is the initialization data input from an external EEPROM. When EDIN is high, this pin is the initialization data input from a microcontroller. Equalizer bias resistor input. An external 9.53ky, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function.
26 (22, 23) 27 (24, 25) 28 (26, 27) 29 (28)
DGND4 DVCC5 DGND5 T4EN
30 (29)
T4FAIL
31 (30)
EDIN
32 (31)
SEL10HD
33 (32)
SEL10FD/ ECLK
34 (33) 35 (34)
AVCC3 SEL100T4/ EDOUT
36 (35)
RGMSET
5
ML6692
PIN DESCRIPTION
37 (36) RTSET (Continued) Transmit level bias resistor input. An external 2.49kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. Analog ground. Transmit twisted pair outputs. This differential current output pair drives FLP waveforms and MLT-3 waveforms into the network coupling transformer in 100BASE-TX mode, or 10BASE-T waveforms in 10BASE-T mode. Analog ground. Analog +5V power supply. 100BASE-TX link activity open-drain output. LINK100 pulls low when there is 100BASETX activity at TPINP/N in 100BASE-TX or auto-negotiation modes. This output is capable of driving an LED directly. Receive twisted pair inputs. This differential input pair receives 100BASE-TX, FLP, or 10BASE-T signals from the network. Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver, typically (VCC - 1.26)V. Full duplex enabled TTL output. This output is high during the auto-negotiation process, it's low when auto-negotiation is reset (power-up, reset bit, restart auto-negotiation bit, power down bit, or link loss) and follows the duplex status otherwise. It drives the ML2653's FD input, and prevents the ML2653 from attempting to transmit during autonegotiation. For 10BASE-T transceivers without pin-selectable MAU loopback disable, DUPLEX can be used to disable the 10BASE-T transceiver's receive and collision outputs to the controller during auto-negotiation.
38 (37, 38)
AGND3
39, 40 (39, 40) TPOUTN/P
41 (41, 42) 42 (43) 43 (44)
AGND2 AVCC2 LINK100
44, 45 (45, 46) 46 (47) 47 (48)
TPINN/P CMREF DUPLEX
48, 49 (50, 51) 10BTTXINN/P 10BASE-T transmit waveform inputs. The ML6692 presents a linear copy of the input at 10BTTXINP/N to the TPOUTP/N outputs when the ML6692 functions in 10BASE-T mode. Signals presented to these pins must be centered at VCC/2 and have a single ended amplitude of 0.25V. 50 (53) 51 (54) 10BTRCV 10BASE-T receive activity TTL input. The external 10BASE-T transceiver drives this pin high to indicate 10BASE-T packet reception from the network.
10BTLNKEN 10BASE-T link control TTL output. This output is low if the ML6692 is in 10BASE-T mode, or if the auto-negotiation function indicates to the 10BASE-T PMA to scan for carrier. This output is high if the 10BASE-T PMA should be disabled. AVCC1 Analog +5V power supply.
52 (55)
6
ML6692
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range .................. GND -0.3V to 6V Input Voltage Range Digital Inputs ...................... GND -0.3V to VCC +0.3V TPINP, TPINN, 10BTTXNP, 10BTTXINN, ....................... ........................................... GND -0.3V to VCC +0.3V Output Current TPOUTP, TPOUTN .............................................. 60mA All other outputs ................................................. 10mA Junction Temperature .............................................. 150C Storage Temperature .............................-65C to +150C Lead Temperature (Soldering, 10 sec) ..................... 260C Thermal Resistance (qJA) PLCC ............................................................... 40C/W TQFP ............................................................... 52C/W
OPERATING CONDITIONS
VCC Supply Voltage ............................................ 5V 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA , Ambient temperature .............................. 0C to 70C RGMSET .................................................... 9.53kW 1% RTSET ........................................................ 2.49kW 1% Receive transformer insertion loss ...................... <-0.5dB
DC ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified (Note 1).
SYMBOL RECEIVER V ICM V ID RIDR I ICM IRGM IRT TPINP/N Input Common-Mode Voltage (CMREF) TPINP-TPINN Differential Input Voltage Range TPINP-TPINN Differential Input Resistance TPINP/N Common-Mode Input Current RGMSET Input Current RTSET Input Current RGMSET = 9.53kW RTSET = 2.49kW 130 500 -3.0 10.0k +10 VCC - 1.26 3.0 V V W A A A PARAMETER CONDITIONS MIN TYP MAX UNITS
LED OUTPUT (LINK100) IOLS IOHS Output Low Current Output Off Current 5 10 mA A
TRANSMITTER I TD100 I TD10 ITOFF ITXI TPOUTP/N 100BASE-TX Mode Differential Output Current TPOUTP/N 10BASE-T Mode Differential Output Current TPOUTP/N Off-State Output TPOUTP/N Differential Output Current Imbalance RL = 200, 1% RL = 200, 1% Note 2, 3 19 55 0 60 21 65 1.5 500 mA mA mA A
7
ML6692
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TRANSMITTER (Continuied) XERR X CMP100 V OCM10 V ICM10 TPOUTP/N Differential Output Current Error TPOUTP/N 100BASE-X Output Current Compliance Error TPOUTP/N 10BASE-T Output Voltage Compliance Range 10BTTXNN/P Input Common-Mode Voltage Range VOUT = VCC; Note 3 VOUT = VCC 2.2V; referred to IOUT at VCC ITD10 remains within specified values -5.0 +5.0 %
(Continued)
CONDITIONS MIN TYP MAX UNITS
-2.0 VCC - 2.7 VCC/2 - 0.3
+2.0 VCC + 2.7 VCC/2 + 0.3
% V V
POWER SUPPLY CURRENT I CC100 I CC10 ICCOFF I CCAUTO Supply Current, 100BASE-TX Operation, Transmitting Supply Current, 10BASE-T Operation, Transmitting Supply Current Power Down Mode Supply Current During Auto-negotiation Current into all VCC pins Current into all VCC pins Current into all VCC pins Current into all VCC pins 240 200 40 300 70 20 300 mA mA mA mA
TTL INPUTS (TXD<3:0>, TXCLKIN, MDC, MDIO, TXEN, TXER, 10BTRCV, T4FAIL) VIL VIH IIL IIH Input Low Voltage Input High Voltage Input Low Current Input High Current IIL = -400A IIH = 100A VIN = 0.4V VIN = 2.7V 2.0 -200 100 0.8 V V A A
MII TTL OUTPUTS (RXD<3:0>, RXCLK, RXDV, RXER, CRS, COL, MDIO, TXCLK) VOLT V OHT Output Low Voltage Output High Voltage IOL = 4mA IOH = -4mA 2.4 0.4 V V
NON-MII TTL OUTPUTS (DUPLEX, T4EN, 10BTLNKEN) VOLT V OHT Output Low Voltage Output High Voltage IOL = 1mA IOH = -0.1mA 2.4 0.4 V V
CMOS INPUTS (EDIN, SEL10HD, SEL10FD/ECLK, SEL100T4/EDOUT) V ILC V IHC Input Low Voltage Input High Voltage 0.8 x VCC 0.2 x VCC V V
CMOS OUTPUTS (SEL10FD/ECLK) VOLC V OHC Output Low Voltage Output High Voltage IOL = 2mA IOL = -2mA 0.9 x VCC 0.1 x VCC V
V
8
ML6692
AC ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified
SYMBOL RECEIVER V ICM TPINP/N Input Common-Mode Voltage (CMREF) VCC - 1.26 V PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSMITTER (NOTE 3) tTR/F tTM t TDC tTJT XOST tCLK tTXP RECEIVER tRXDC tRXDR Receive Bit Delay (CRS) Receive Bit Delay (RXDV) Note 9 Note 10 15.5 25.5 bit times bit times TPOUTP-TPOUTN Differential Rise/Fall Time TPOUTP-TPOUTN Differential Rise/Fall Time Mismatch TPOUTP-TPOUTN Differential Output Duty Cycle Distortion TPOUTP-TPOUTN Differential Output Peak-to-Peak Jitter TPOUTP-TPOUTN Differential Output Voltage Overshoot TXCLKIN - TXCLK Delay Transmit Bit Delay Note 8 Notes 5, 6; for any legal code sequence Notes 5, 6; for any legal code sequence Notes 4, 6 Note 6 Notes 6, 7 6 3.0 -0.5 -0.5 300 5.0 0.5 0.5 1400 5 11 10.5 ns ns ns ps % ns bit times
MII (MEDIA-INDEPENDENT INTERFACE) XBTOL t TPWH t TPWL tRPWH tRPWL t TPS TX Output Clock Frequency Tolerance TXCLKIN pulse width HIGH TXCLKIN pulse width LOW RXCLK pulse width HIGH RXCLK pulse width LOW Setup time, TXD<3:0> Data Valid to TXCLK Rising Edge (1.4V point) Hold Time, TXD<3:0> Data Valid After TXCLK Rising Edge (1.4V point) Time that RXD<3:0> Data are Valid Before RXCLK Rising Edge (1.4V point) Time that RXD<3:0> Data are Valid After RXCLK Rising Edge (1.4V point) RXCLK 10% - 90% Rise Time RXCLK 90%-10% Fall Time 25MHz frequency -100 14 14 14 14 13 +100 ppm ns ns ns ns ns
t TPH
0
ns
tRCS
10
ns
tRCH
10
ns
tRPCR tRPCF
6 6
ns ns
9
ML6692
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS MDC-MDIO (MII MANAGEMENT INTERFACE) tSPWS Write Setup Time, MDIO Data Valid to MDC Rising Edge 1.4V Point Write Hold Time, MDIO Data Valid After MDC Rising Edge 1.4V Point Read Setup Time, MDIO Data Valid to MDC Rising Edge 1.4V Point Read Hold time, MDIO Data Valid After MDC Rising Edge 1.4V Point Period of MDC Pulsewidth of MDC Positive or negative pulses 10 ns
tSPWH
10
ns
tSPRS
100
ns
tSPRH
0
ns
tCPER t CPW
400 160
ns ns
INITIALIZATION INTERFACE t PW1 t PW2 tPER1 t DV1 tPER2 t PW3 t PW4 tS1 t H1 ECLK Positive Pulsewidth ECLK Negative Pulsewidth ECLK Period, EEPROM Mode EDOUT Data Valid Time After ECLK Rising Edge ECLK period ECLK Positive Pulsewidth ECLK Negative Pulsewidth ECLK Data Setup Time ECLK Data Hold Time EDIN floating (EEPROM Mode) EDIN floating (EEPROM Mode) EDIN floating (EEPROM Mode) EDIN floating (EEPROM Mode) EDIN high (Microcontroller Mode) EDIN high (Microcontroller Mode) EDIN high (Microcontroller Mode) EDIN high (Microcontroller Mode) EDIN high (Microcontroller Mode) 5000 2000 2000 10 10 900 900 1800 900 ns ns ns ns ns ns ns ns ns
Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2. Measured using the test circuit shown in fig. 1, under the following conditions: RLP = 200W, RLS = 49.9W, RTSET = 2.49kW. All resistors are 1% tolerance. Note 3. Output current amplitude is IOUT = 40W 1.25V/RTSET. Note 4. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence. Note 5. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the external network coupling transformer and EMI/RFI emissions filter. Note 6. Differential test load is shown in fig. 1 (see note 2). Note 7. Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge. Note 8. From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI. Note 9. From first bit of J at the MDI, to CRS. Note 10. From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high.
10
ML6692
VCC TPOUTP RLP 200 2:1 1
RLP 200 TPOUTN RLS 50
2 RLS 50
Figure 1.
TXCLKIN tTPWH tTPWL
TXCLK
TXD<3:0> TXER TXEN tTPS tTPH
Figure 2. MII Transmit Timing
tRPCR RXCLK tRPCF
RXD<3:0> RXER RXDV tRCS tRCH
Figure 3. MII Receive Timing
MDC
MDIO
tSPWS
tSPWH
Figure 4. MII Management Interface Write Timing
tCPER
MDC tSPRS tSPRH tCPW tCPW
MDIO
Figure 5. MII Management Interface Read Timing
11
ML6692
FUNCTIONAL DESCRIPTION
TRANSMIT SECTION 100BASE-TX Operation The transmitter includes everything necessary to accept 4-bit data nibbles clocked in at 25MHz at the MII and output scrambled, 5-bit encoded MLT-3 signals into twisted pair at 100Mbps. The on-chip transmit PLL converts a 25MHz TTL-level clock at TXCLKIN to an internal 125MHz bit clock. TXCLK from the ML6692 clocks transmit data from the MAC into the ML6692's TXD<3:0> input pins upon assertion of TXEN. Data from the TXD<3:0> inputs are 5-bit encoded, scrambled, and converted from parallel to serial form at the 125MHz clock rate. The serial transmit data is converted to MLT-3 3-level code and driven differentially out of the TPOUTP and TPOUTN pins at nominal 2V levels with the proper loads. The transmitter is designed to drive a center-tapped transformer with a 2:1 winding ratio, so a differential 400y load is used on the transformer primary to properly terminate the 100W cable and termination on the secondary. The transformer's center tap must be tied to VCC. A 2:1 transformer allows using a 20mA output current in 100BASE-TX mode and 60mA in fast link pulse and 10BASE-T modes. Using a 1:1 transformer would have required twice the output current and increased the onchip power dissipation. An external 2.49kW, 1% resistor at the RTSET pin creates the correct output levels at TPOUTP/N. Driving TXER high when TXEN is high causes the H symbol (00100) to appear in scrambled MLT-3 form at TPOUTP/N. The media access controller asserts TXER synchronously with TXCLK rising edge, and the H symbol appears at least once in place of a valid symbol in the current packet. With no data at TXD<3:0> or with the ML6692 in isolate mode (MII Management register bit 0.10 set to a 1), scrambled idle appears at TPOUTP/N. Auto Negotiation and Fast Link Pulses (FLPs) During the auto negotiation process, the transmitter produces nominal 5V fast link pulses (FLP's) at TPOUTP/N (2.5V after 2:1 transformer). When the auto negotiation process is complete, the transmitter either switches over to 100BASE-TX mode, activates the 10BTTXINP/N inputs for 10BASE-T operation with an external 10BASE-T transceiver, or enables a 100BASE-T4 PMA and powers down the on-chip transmitter. 10BASE-T In 10BASE-T mode, the transmitter acts as a linear buffer with a gain of 10. 10BASE-T inputs (Manchester data and normal link pulses) at 10BTTXINP/N appear as full-swing signals at TPOUTP/N in this mode. Inputs to the 10BTTXINP/N pins should have a nominal 0.25V differential amplitude and a common-mode voltage of VCC/2, and should also be waveshaped or filtered to meet the 10BASE-T harmonic content requirements. The ML6692 does not provide any 10BASE-T transmit filtering. The ML2653 10BASE-T physical interface chip provides a waveshaped 10BASE-T output and may be used with a resistive load network for a simple 2-chip 10/100 solution with the ML6692. The ML2653 interfaces to a controller through it's "7-wire" interface. RECEIVE SECTION 100BASE-TX Operation The receiver includes all necessary functions for converting 3-level MLT-3 signals from the twisted-pair media to 4-bit data nibbles at RXD<3:0> with extracted clock at RXCLK. The adaptive equalizer compensates for cable distortion and attenuation, corrects for DC baseline wander, and converts the MLT-3 signal to 2-level NRZ. The receive PLL extracts clock from the equalized signal, providing additional jitter attenuation, and clocks the signal through the serial to parallel converter. The resulting 5-bit nibbles are descrambled, aligned and decoded, and appear at RXD<3:0>. The ML6692 asserts RXDV when it's ready to present properly decoded receive data at RXD<3:0>. The extracted clock appears at RXCLK. Resistor RGMSET sets internal time constants controlling the adaptive equalizer's transfer function. RGMSET must be set to 9.53kW (1%). The receiver will assert RXER high if it detects code errors in the receive data packet, or if the idle symbols between packets are corrupted. COL goes high to indicate simultaneous 100BASE-TX receive and transmit activity (a collision). CRS goes high whenever there is either receive or transmit activity in the ML6692's "station" mode (the default mode; see Initialization Interface section below for more information). In the ML6692's "repeater" mode, CRS goes high only when there is receive activity. Auto Negotiation The 100BASE-TX signal detect circuit in the adaptive equalizer ignores fast and normal link pulses, and will not pass them on to the rest of the receive channel. Instead, FLPs (and NLPs) are recognized and processed by the auto negotiation logic. When the auto negotiation process is complete, either the adaptive EQ and the rest of the 100BASE-TX receive path remain active for 100BASE-TX reception, all the ML6692's receive circuitry is disabled and the external 10BASE-T transceiver is enabled (if it exists), or all the ML6692's 10BASE-T and 100BASE-TX functionality is disabled and an external 100BASE-T4 PMA is enabled. In 10BASE-T or 100BASE-T4 modes, the ML6692 RXD<3:0>, RXC, RXER, RXDV, COL and CRS MII outputs are in high impedance state. See the next section for more information on auto negotiation. Proper connection of the TPIN pins, magnetics, and cable is necessary for proper auto negotiation since the ML6692
12
ML6692
FUNCTIONAL DESCRIPTION
(Continued) With MII Management register bit 0.12 = 0 (auto negotiation disabled) the ML6692 can be forced into a certain mode using bits 0.13 (speed select), bit 0.8 (duplex mode), and pin T4FAIL, as shown in the following table. SPEED DUPLEX SELECT MODE 1 1 1 0 0 1 0 X 1 0 T4FAIL 0 0 1 X X MODE 100BASE-TX Full Duplex 100BASE-TX Half Duplex 100BASE-T4 10BASE-T Full Duplex 10BASE-T Half Duplex does not detect or correct errors in the polarity of fast or normal link pulses. USING THE ML6692 WITH AUTOMATIC LINK CONFIGURATION The ML6692 supports automated link protocol negotiation and configuration. In the ML6692, the auto negotiation state machine checks the receive signal and detects the presence of link pulses in bursts or singly. The auto negotiation state machine then updates the status register in the management logic, and forces the receiver and transmitter to perform the appropriate function, depending on the remote link partner and local port capabilities. If FLP (fast link pulse) bursts are detected, the auto negotiation state machine disables all protocol-specific link detection and drives the transmitter with answering FLP bursts. The auto negotiation state machine then enables the highest common denominator protocol between the local port and the remote link partner. If the highest common denominator technology is 100BASE-TX, the ML6692 100BASE-TX receiver is enabled. If the highest common denominator technology is 10BASE-T, the auto negotiation state machine disables the ML6692 100BASE-TX receiver and enables 10BASE-T output from the ML6692's transmitter. If the highest common denominator technology is 100BASE-T4, the ML6692's transmitter and receiver are disabled and the external 100BASE-T4 transceiver is enabled. The ML6692 supports the parallel detection function by checking simultaneously for normal or fast link pulses, 100BASE-TX signal activity at TPINP/N, or indication of 100BASE-T4 activity from the external 100BASE-T4 transceiver. If one of the locally supported protocols is detected, that protocol is enabled and all others are disabled. If the local port lacks 10BASE-T capability and NLPs are detected, the local auto negotiation state machine disables transmission of all link pulses to force the far-end station into link fail, and restarts autonegotiation. The ML6692 takes a number of specific actions depending on which supported technology is selected. If the 100BASE-TX technology is selected, the ML6692 switches its clock recovery circuit from tracking the local 125MHz bit clock to tracking the equalized, decoded receive signal, descrambles, decodes and finds the packet boundaries of the signal, asserts RXDV, and presents the decoded receive data nibbles at RXD<3:0>. The ML6692 will also drive 10BTLNKEN and T4EN high to deactivate external 10BASE-T and 100BASE-T4 transceivers. If the 100BASE-T4 transceiver detects activity, it will drive the ML6692's T4FAIL pin high and the ML6692 will place its receiver and transmitter in an idle state, and will drive 10BTLNKEN high.
ML6692 PHY MANAGEMENT FUNCTIONS The ML6692 has management functions controlled by the register locations given in Tables 2-6. There are five 16-bit MII Management registers, with several unused locations. Unused locations are generally reserved for future use. Register 0 (Table 2) is the basic control register (read/ write). Register 1 (Table 3) is the basic status register (read-only). Register 4 (Table 4) is the auto-negotiation capability advertisement register. Register 5 (Table 5) is the auto-negotiation link partner ability register (what the far-end station is capable of; read-only). Register 6 (Table 6) is the auto-negotiation expansion register (indicates some additional auto-negotiation status information; readonly). Note that status bits 1.11-1.12 (10BASE-T capability) and 1.15 (100BASE-T4) depend on the values programmed through the Initialization Interface. See the initialization interface section for programming information. The ML6692 powers on with all management register bits set to their default values. The ML6692's auto negotiation status and control register addresses and functions match those described for the MII in IEEE 802.3u section 22. IEEE 802.3u specifies the management data frame structure in section 22.2.4.4. See the IEEE 802.3u Specification section 28 for auto negotiation state machine definition, FLP timing, and overall operation. See IEEE 802.3u section 22.2.4 for a discussion of MII management functions and status/control register definitions.
13
ML6692
INITIALIZATION INTERFACE
The ML6692 has an Initialization Interface to allow register programming that is not supported by the MII Management Interface. The intitialization data is loaded at power-up and cannot be changed afterwards. The pin EDIN selects one of three possible programming modes. The Initialization Register bit assignment is shown in Table 1. EEPROM PROGRAMMING With EDIN floating (set to a high impedance), the ML6692 reads the 16 configuration bits from an external serial EEPROM (93LC46 or similar) using the industrystandard 3-wire serial I/O protocol. After power up, the ML6692 automatically generates the address at EDIN and the clock at ECLK to read out the 16 configuration bits. The EEPROM generates the configuration bit stream at EDOUT, synchronized with ECLK. Interface timing is shown in Figure 6. It is important to note that the ML6692 expects LSBs first, whereas the 93LC46 shifts MSBs out first. Therefore, the data pattern must be reversed before programming it into the EEPROM. MICROCONTROLLER PROGRAMMING With EDIN high, the ML6692 expects the 16 configuration bits transfered directly at EDOUT, synchronized with the first 16 clock rising edges provided externally at ECLK after power-up. This mode is useful with a small microcontroller; one controller can program several ML6692 parts by selectively toggling their ECLK pins. Interface timing is shown in Figure 7. ML6692 HARD-WIRED DEFAULT With EDIN low, the SEL10HD, SEL10FD, and SEL100T4 pins set their corresponding bits in the management status register, and the ML6692 responds to MII PHYAD 00000 only.
FUNCTION OF RELATED PINS EDIN Floating (EEPROM ADDR) High Low MODE EEPROM Microcontroller Hardwired SEL10FD/ECLK ECLK (Output Clock to EEPROM) SEL100T4/EDOUT EDOUT (Input Data from EEPROM) SEL10HD No Affect No Affect SEL10HD (Initialization bit 10)
ECLK (Input Clock EDOUT (Input Data from Microcontroller) from Microcontroller) SEL10FD (Initialization bit 9) SEL100T4 (Initialization bit 8)
tPW1 ECLK (DRIVEN BY ML6692) 01 02 03 04 05 06 07
tPW2 08 09 10
tPER1 11 12 13 26
EDIN (DRIVEN BY SB ML6692) 1 EDOUT (DRIVEN BY EEPROM)
OP1 1
OP0 0
A5 0
A4 0
A3 0
A2 0
A1 0
A0 0
D0
D1 tDV1
D2
D3
D14
D15
16 BITS DATA ADDRESS
Figure 6. EEPROM Interface Timing
ECLK (INPUT TO ML6692) EDOUT (INPUT TO ML6692)
01
tPW3 02
tPER2 16 tPW4
tH1
tS1
Figure 7. Microcontroller Mode Interface Timing
14
ML6692
INITIALIZATION INTERFACE REGISTER
BIT(S) I.15 I.14 I.13 I.12 I.11 I.10 PHY A4 PHY A3 PHY A2 PHY A1 PHY A0 10HDUP NAME DESCRIPTION PHY address bit 4 PHY address bit 3 PHY address bit 2 PHY address bit 1 PHY address bit 0 10BASE-T half duplex initialization bit 1 = 10BASE-T (half-duplex) capability 0 = no 10BASE-T (half-duplex) capability 10BASE-T full duplex initialization bit 1 = 10Mb/s full duplex capability 0 = no 10Mb/s full duplex capability 100BASE-T4 initialization bit 1 = 100BASE-T4 capability 0 = no 100BASE-T4 capability Isolate bit disable (bit 0.10) Repeater mode: when this bit is set to 1, CRS isonly asserted when receiving non-idle signal at TPINP/N, and the ML6692 is forced to half duplex mode R/W DEFAULT 0 0 0 0 0 0
I.9
10FDUP
0
I.8
100T4
0
I.7 I.6
ISODIS REPEATER
0 0
I.5-I.0
Not used Table 1. Initialization Interface Register
Note: Bits I<10:8> are the values for bits 1.11, 1.12 and 1.15 and initial values for bits 4.5, 4.6 and 4.9 of the MII Management Interface.
MII MANAGEMENT INTERFACE REGISTERS
BIT(S) 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6 - 0.0 Reset Loopback Manual speed select (Active when 0.12 = 0) Auto negotiation enable Power down Isolate Restart auto negotiation Duplex mode Collision Test Not Used Table 2. Control Register NAME DESCRIPTION 1 = reset all register bits to defaults 0 = normal operation 1 = PMD loopback mode 0 = normal operation 1 = 100Mb/s 0 = 10Mb/s 1 = enable auto negotiation 0 = disable auto negotiation 1 = power down 0 = normal operation 1 = electrically isolate the ML6692 from MII 0 = normal operation 1 = restart auto negotiation 0 = normal operation 1 = Full duplex select, auto negotiation disabled 0 = Half duplex select, auto negotiation disabled 1 = enable COL signal test 0 = normal operation R/W R/W, SC R/W R/W R/W R/W R/W R/W, SC R/W R/W DEFAULT 0 0 1 1 0 1 0 0 0
15
ML6692
MII MANAGEMENT INTERFACE REGISTERS
BIT(S) 1.15 1.14 1.13 1.12 1.11 NAME 100BASE-T4 100BASE-TX full duplex 100BASE-TX half duplex 10Mb/s full duplex 10BASE-T (half duplex) (Continuied) R/W RO RO RO RO RO DEFAULT 100T4 (bit I.8) 1 1 10FDUP (Bit I.9) 10HDUP (Bit I.10) DESCRIPTION 1 = 100BASE-T4 capability 0 = no 100BASE-T4 capability 1 = full duplex 100BASE-TX capability 0 = No full duplex 100BASE-TX capability 1 = half duplex 100BASE-TX capability 0 = no half duplex 100BASE-TX capability 1 = full duplex 10Mb/s capability 0 = No full duplex 10Mb/s capability 1 = 10BASE-T (half duplex) capability 0 = No 10BASE-T (half duplex) capability 1 = auto negotiation process complete 0 = auto negotiation not complete 1 = auto negotiation capability available 0 = auto negotiation capability not available 1 = one and only one PHY-specific link is up 0 = link is down 1 = extended register capabilities 0 = basic register set only Table 3. Status Register
1.10 - 1.6 Not Used 1.5 1.4 1.3 1.2 1.1 1.0 Auto negotiation compl. Not Used Auto negotiation ability Link status Not Used Extended capability RO 1 RO RO/LL 1 latch low after link fail until read RO 0
BIT(S) 4.15 4.14 4.13
NAME Next Page Reserved Remote fault
DESCRIPTION 1 = additional link code word pages 0 = no additional pages Write as zero, ignore on read 1 = remote wire fault detected 0 = no remote wire fault detected
R/W RO RO R/W
DEFAULT 0
0
4.12-4.10 Reserved 4.9 4.8 4.7 4.6 4.5 4.4-4.1 4.0 100BASE-T4 capability 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Selector field Selector field
(Not used at present)
1 = 100BASE-T4 capability 0 = no 100BASE-T4 capability 1 = 100BASE-TX full duplex capability 0 = no 100BASE-Tfull duplex 1 = 100BASE-TX capability 0 = no 100BASE-TX capability 1 = 10BASE-T full duplex capability 0 = no 10BASE-T full duplex capability 1 = 10BASE-T capability 0 = no 10BASE-T capability All these bits are 0 for 802.3 LANs This bit is a 1 for 802.3 LANs Table 4. Advertisement Register R/W R/W R/W R/W R/W RO RO 100T4 (Bit I.8) 1 1 10FDUP (Bit I.9) 10HDUP (Bit I.10) 0 1
16
ML6692
MII MANAGEMENT INTERFACE REGISTERS
BIT(S) 5.15 5.14 NAME Next Page Acknowledge (Continuied) R/W RO RO DEFAULT X X DESCRIPTION 1 = additional link code word pages 0 = no additional pages 1 = link partner's successful receipt of local station code 0 = no link partner reception of local station code 1 = remote wire fault detected 0 = no remote wire fault detected
5.13
Remote fault
R/W
X
5.12-5.10 Reserved 5.9 5.8 5.7 5.6 5.5 5.4-5.1 5.0 100BASE-T4 capability 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Selector field Selector field
(Not used at present)
1 = 100BASE-T4 capability 0 = no 100BASE-T4 capability 1 = 100BASE-TX full duplex capability 0 = no 100BASE-TX full duplex 1 = 100BASE-TX capability 0 = no 100BASE-TX capability 1 = 10BASE-T full duplex capability 0 = no 10BASE-T full duplex capability 1 = 10BASE-T capability 0 = no 10BASE-T capability All these bits are 0 for 802.3 LANs This bit is a 1 for 802.3 LANs Table 5. Link Partner Register R/W R/W R/W R/W R/W RO RO
X
X X X X X X X
BIT(S) 6.15-6.5 6.4
NAME Reserved; not used Multiple link fault
DESCRIPTION 1 = more than one receiving protocol indicates link OK 0 = no multiple link faults 1 = link partner supports next page 0 = link partner has no next page 1 = local port supports next page 0 = local port has no next page 1 = 3 identical, consecutive link code words received 0 = 3 identical, consecutive link code words NOT received
R/W RO; reset on read RO RO RO; reset on read
DEFAULT 0 0
6.3 6.2 6.1
Link partner next page able Next page able Page received
0 0 0
6.0
Link partner auto neg. capable 1 = link partner has auto negotiation capability 0 = link partner has NO auto negotiation capability
RO
0
NOTE: All unnamed or unused register locations will return 0 values when accessed. KEY: LL = latch low until read, R/W = read/write, RO = read only, SC = self-clearing.
Table 6. Expansion Register
17
7-WIRE INTERFACE
TXEN
TXD0
TXD1
TXD2
AGND1
AVCC1
TXCLKIN
10BTRCV
DUPLEX
TXC C1 8 TXER CMREF 46 TPINP 45 TPINN 44 LINK100 43 AVCC2 42 AGND2 41 TPOUTP 40 TPOUTN 39 AGND3 38 RTSET 37 RGMSET 36 SEL100T4/EDOUT 35 AVCC3 34 R1 R2 9 TXCLK 10 RXD3 11 DGND1 12 RXD2 13 DVCC1 14 RXD1 15 DGND2 16 RXD0 17 RXCLK 18 CRS 19 COL 20 DGND3
TXD3
10BTTXINP
10BTLINKEN
10BTTXINN
RXDV
DVCC2
RXER
MDC
MDIO
DGND4
DVCC5
DGND5
T4EN
T4FAIL
EDIN
SEL10HD
RXER 21 22
SEL10FD/ ECLK
MII INTERFACE
18
DVCC
14 13 12
AVCC FB1
18
17
16
15
FD
LTP
CS0
COL
VCC
VCC
RPOL
R12 NC D4 NC R5 34 FB2 R23 75 C15 4 3 R4 34 1 R6 23.7 C3 C9 C10 C6 C4 RX- RX+ LPBK CLK NC TX-
5 6 7 8 9 10 11
ML6692
19
CS1
+ C11 C12
+ C5
COL
20
CS2
RXE
21
RXE
RXC
22
RXC 2
RXD
23
ML2653 U3 U2
RXD
NC
24
XMT/RCV
NC
TX+ GND GND
25
RSL
TXD
TXC
26
RTX
2 3 4
27
TXE
28
1
X1 D1 7 2 R3 R10 C7 R11 1 52 51 50 49 48 47 6 5 4 3 R26
1:1 1 2 3 4 5 6 7 8 RXTP- TXTP+ TXTP- RXTP+
TXE
TXD

R16 L1 R8 R15
LPBK
R7 40.2k
RJ45 SHIELD GROUNDED 2:1 R22 R9 R19 L2 R18 R17
CRS
ML6692 U1
COL
U5
R21
R20
Table 8. 10/100 BASE-T Application Circuit
C8 23 24 25 26 27 28 29 30 31 32 33 NC 4 5 3 U4 6 7 8 2 1 14 1 13 12 11 10 U6 23 4 5
TXD3
TXD2
TXD1
TXD0
C2
TXEN
TXCLK
TXER
D6 R14 C14
RXCLK
RXDV
RXD0
RXD1
RXD2
9 6
8 7
D5 R13 C13
D2 D3 R24 R25
RXD3
MDC

MDIO
ML6692
ML6692 SCHEMATIC
Figure 8 shows a general 10BASE-T and 100BASE-TX design using the ML2653 (10BASE-T PHY) and ML6692 (100BASE-TX PHY). The inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6692, and improves the Bit Error Rate (BER) performance of the board. We recommend having a 0.1F Cap on every VCC pin as indicated by C3, 4, 9-12. Also, we recommend splitting the AVCC, AGND and DGND. It is recommended that AGND and DGND planes are large enough for low inductance. If splitting the two grounds and keeping the ground planes large enough is not possible due to board space, you could join them into one larger ground plane.
ML6692 PARTS LIST
COMPONENT U1 U2 U3 U4 U5 U6 X1 FB1, FB2 L1, L2 R1 R2 R3, R12, R24, R25 R4, R5* R6 R7 R8, R9, R26 R10, R11 R13, R14 R15-R20 R21, R22 R23 C1, C3, C4, C8-12, C15 C5, C6 C7 C2 C13, C14 D1-D4 DESCRIPTION ML6692 52-Pin PLCC surface mount Can Crystal Oscillator, 25MHz 4-pin surface mount ML2653 28-pin PLCC surface mount 93LC46 8-pin PLCC surface mount EEPROM BEL Transformer Module 5558-1287-02, or XFMRS Inc. XF6692TX, or Valor ST6129 (not pin compatible) HEX Inverter 74HC04 20MHz XTAL surface mount Fair-Rite SM Bead P/N 2775019447 130nH inductors rated at 50MHz 2.49kW 1% 1/8W surface mount 9.53kW 1% 1/8W surface mount 750W 5% 1/8W surface mount 34.0W 1% 1/8W surface mount 23.7W 1% 1/4W surface mount 40.2kW 1% 1/8W surface mount 200W 1% 1/8W surface mount 100W 1% 1/8W surface mount 100kW 10% 1/8W surface mount 49.9W 5% 1/8W surface mount 75W 5% 1/8W surface mount 75W 1% 1/4W surface mount 0.1F Ceramic Chip Cap 0.01F Ceramic Chip Cap 10F Tantalum Cap. 10pF Cap Board layer Cap (2V rated) 22nF Cap LED Diodes
Refer to ML2653 data sheet for CS2, CS1, and CS0 configuration * These resistors need to be tuned to provide a 500mVP-P amplitude single ended signal to the ML6692 inputs.
19
ML6692
PHYSICAL DIMENSIONS
inches (millimeters)
Package: Q52 52-Pin PLCC
0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22) 14
PIN 1 ID 0.750 - 0.754 0.785 - 0.795 (19.05 - 19.15) (19.94 - 20.19) 0.600 BSC (15.24 BSC) 0.690 - 0.730 (17.53 - 18.54)
40
27 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
Package: H64-10 64-Pin (10 x 10 x 1mm) TQFP
0.472 BSC (12.00 BSC) 0.394 BSC (10.00 BSC) 49 0 - 8 0.003 - 0.008 (0.09 - 0.20)
1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC)
33 17 0.020 BSC (0.50 BSC) 0.007 - 0.011 (0.17 - 0.27) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05)
0.018 - 0.030 (0.45 - 0.75)
SEATING PLANE
20
ML6692
PHYSICAL DIMENSIONS
inches (millimeters)
ORDERING INFORMATION
PART NUMBER ML6692CH ML6692CQ TEMPERATURE RANGE 0C - 70C 0C - 70C PACKAGE 64 Pin Thin Quad Flat Pack (TQFP) 52 Pin Plastic Leaded Chip Carrier (PLCC)
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DS6692-02
21

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